Computer systems typically include more than one bus, each bus having attached devices which communicate locally with each other. Often, system busses and peripheral busses use different sets of standard protocols or rules to conduct data transfers between the different devices that are connected thereover. Devices for translating data that is transferred from one bus architecture to another bus architecture are often called bridges. To permit system-wide communications between devices on different bus systems, bus-to-bus bridges match the communications protocol of one bus architecture with that of another bus architecture.
Presently, "local busses" are operated in such a manner as to be more closely associated with central processor operations and are capable of running at speeds that approximate the speed of the central processor. One popular type of "local bus" architecture is the "peripheral component interconnect" (PCI) bus. A system using a PCI bus includes, in addition to the physical PCI bus, a first bridge circuit which provides interface control of transfers of data among devices connected to the PCI bus.
A second bridge circuit (also called a bus controller) provides an interface for transfer of data between a further bus system and the PCI bus. Thus, the arrangement is such that devices on the PCI bus transfer data to and receive data via the first bridge, while devices coupled to the second bus system transfer and receive data through the second bridge (or bus controller). The two bridges communicate with each other and enable data transfers between devices connected to the PCI bus and the second bus system.
Currently, a widely used bus system architecture for connecting host processors to peripheral devices, such as memory subsystems, is one which adheres to the small computer system interconnect (SCSI) protocol. The prior art includes a number of teachings regarding methods for interconnecting SCSI bus systems to PCI bus systems. Examples of such teachings can be found in U.S. Pat. No. 5,634,033 to Stewart et al. and U.S. Pat. No. 5,522,050 to Amini et al. Further SCSI bus interface control systems can be found in U.S. Pat. No. 5,454,085 to Gajjar et al., U.S. Pat. No. 5,550,991 to Keener et al. and U.S. Pat. No. 5,519,883 to White et al.
Notwithstanding the effectiveness of bridges in providing data interfaces between different bus systems, transfers of such data are time consuming and slow the overall operation of the system. This is especially true when short messages are required to be transferred between devices coupled to a PCI bus, and thence via a PCI bridge to a secondary bus controller and a host processor. Each such message transfer requires a PCI bridge to capture the PCI bus, configure a message for transmission thereover, dispatch the message, etc., etc. Just the set up time to enable either dispatch or receipt of a short message requires considerable processing time and acts to delay other system functions.
An example of such a message is a status indication that is issued by a memory subsystem to indicate the success or failure of a read/write action. Such a status message is dispatched to the host processor which initiated the read or write request.
Accordingly, it is an object of this invention to improve the processing efficiency of data transfers in a computing system which employs multiple bus systems that are used to carry relatively short message data.